1. Field of the Invention
The present invention relates to a level shifter functioning as device input buffer for a semiconductor memory device and, more particularly, to a high speed scalable level shifter which optimizes power consumption.
The present application is based on Korean Patent Application No. 69195/1996 which is incorporated herein by reference.
2. Description of the Related Art
Level shifters for converting a signal having an input voltage level into a signal having a predetermined voltage level are commonly used as input buffers in semiconductor memory devices. Semiconductor memory devices which use an internal operating voltage which is typically different than an external or system operating voltage such as static random access memory devices (SRAMs) are in widespread use due in part to the lower operating voltage requirements of modern central processing units. Level shifters which receive a signal having a variable input voltage within a constant range and which shift the variable input voltage to an internal operating voltage level of the semiconductor memory device are called scalable input buffers.
FIG. 1 is a circuit diagram of a conventional scalable level shifter. The level shifter shown in FIG. 1 comprises inverter I1 and a shift latch which includes PMOS transistors 3 and 4 and NMOS transistors 1 and 2. PMOS transistors 3 and 4 are cross-coupled, that is, the gate of PMOS transistor 3 is connected to the drain of PMOS transistor 4. Likewise, the gate of PMOS transistor 4 is connected to the drain of PMOS transistor 3. The source terminals of NMOS transistors 1 and 2 are connected to a second power supply, typically, ground. The gate of NMOS transistor 1 is connected to the input terminal of inverter I1. The gate of NMOS transistor 2 is connected to the output terminal of inverter I1. Inverter I1 includes PMOS transistor 5 and NMOS transistor 6. Inverter I1 receives an address or a data input within a constant range of 1.8-2.5 volts through input terminal AI and a power supply voltage within the same range supplied from an external central processing unit through external power supply voltage input terminal VDDI.
The level shifter shown in FIG. 1 generates a current at a transition interval during which the voltage level of the input terminal AI changes from a logic LOW to a HIGH or from a logic HIGH to a logic LOW. The level shifter of FIG. 1 cuts off the current during a non-transition interval, that is, when the voltage level of the input terminal is not changing logic states. For example, if output signal ai is changed from a logic HIGH to a logic LOW when a logic HIGH is applied to the gate of NMOS transistor 2, PMOS transistor 4 and NMOS transistor 2 turn on allowing current to flow from internal power supply VDD to ground. This current flow results in output aib changing from a logic HIGH to a logic LOW level. It should be apparent to one skilled in the art that there is no need to provide internal power supply VDD to the source of PMOS transistor 4 once output ai has changed to a logic HIGH.
However, since the amount of the current flowing through PMOS transistor 4 and NMOS transistor 2 during the transition interval is proportional to the operating speed of the device, if the current is large, the performance of the chip deteriorates. Moreover, chip size becomes difficult to optimize when internal power supply VDD must be kept within the range of 1.8-2.5 volts. This is so because as internal power supply VDD increases, the driving capability of PMOS transistors 3 and 4 increases making it difficult to rapidly vary the states of outputs ai and aib. In other words, if the gate of PMOS transistor 3 and the gate of PMOS transistor 4 is grounded through either NMOS transistor 2 or 1, respectively, turning on, the voltage difference between the gate of PMOS transistor 3 and the source of PMOS transistor 4 or between the gate of PMOS transistor 4 and the source of PMOS transistor 3 increases making it difficult to rapidly vary outputs aib and ai.
Therefore, a need exists for a high speed scalable level shifter which optimizes power consumption.